MMCReplay.txt

From ReplayResources
Jump to navigationJump to search

mmcreplay.txt was copied unchanged from the original file.

This seems to be an earlier version of what became MMC Replay Programmers Manual v0.7

****************************************
* MMC Replay Hardware Description V0.8 *
*     (C) 2008 by Oliver Achten        *
****************************************
 
**** PRELIMINARY !!! ****
 
Overview
--------
The MMC Replay card is an combination of the famous Retro Replay & MMC64 C64
hardware products from Individual Computers into one single cartridge. It is 99%
compatible with existing software written for both products, and its behaviour
is modeled as if a Retro Replay card is plugged into the expansion connector of 
a MMC64 card. However, this hardware introduces several additional features, 
which greatly enhance the usefulness of both products this hardware represents.
 
Features
--------
512KB FLASH rom
512KB SRAM
1KB Serial EEPROM for configuration storage
SPI Interface to access MMC / Secure Digital cards
Clockport to connect additional hardware
Freezer functionality (Action Replay / Retro Replay compatible)
Reset button
 
Register map
------------
 
<> = to be implemented
 
$DE00:	RR control register write
		-----------------------------
		bit 0:	GAME line (W)
		bit 1:	EXROM line (W)
		bit 2:	1 = disable RR (W) (*)
		bit 3:	bank address 13 (W)
		bit 4:	bank address 14 (W)
		bit 5:	0 = rom enable, 1 = ram enable (W)
		bit 6:	1 = exit freeze mode (W)
		bit 7:	bank address 15 (W)
 
(*) bit can be reset by setting bit 6 of $df12
 
$DE01:	extended RR control register write
		--------------------------------------
		bit 0:	0 = disable clockport, 1 = enable clockport (W)
		bit 1:	0 = disable io ram banking, 1 = enable io ram banking (W)
		bit 2:	0 = enable freeze, 1 = disable freeze (W)
		bit 3:	bank address 13 (mirror of $DE00) (W)
		bit 4:	bank address 14 (mirror of $DE00) (W)
		bit 5:	0 = enable MMC registers, 1 = disable MMC registers (W)(*)
		bit 6:	0 = ram/rom @ DFxx, 1 = ram/rom @ $DExx (W)
		bit 7:	bank address 15 (mirror of $DE00) (W)
 
(*) Can only be written when bit 6 of $DF12 is 1. Register becomes effective
		when bit 0 of $DF11 is 1.
 
$DE00 / $DE01: RR control register read
		-----------------------------------
		bit 0:	0 = Flash write protected, 1 = Flash write enabled
		bit 1:	0 = always map first ram bank in i/o space, 1 = enable io ram banking (R)
		bit 2:	1 = freeze button pressed
		bit 3:	bank address 13 (R)
		bit 4:	bank address 14 (R)
		bit 5:	** ALWAYS 0 **
		bit 6:	0 = ram/rom @ DFxx, 1 = ram/rom @ $DExx (R)
		bit 7:	bank address 15 (R)
 
$DE02 - $DE0F: Clockport memory area (when enabled)
		-----------------------------------------------
 
$DF10:	MMC SPI transfer register
		-----------------------------
		byte written is sent to the card & response from the card is read here
 
$DF11:	MMC control register
		------------------------
		bit 0:	0 = MMC BIOS enabled, 1 = MMC BIOS disabled (R/W) (*)
		bit 1:	0 = card selected, 1 = card not selected (R/W) (**)
		bit 2:	0 = 250khz transfer, 1 = 8mhz transfer (R/W)
		bit 3:	** ALWAYS 0 **
		bit 4:	** ALWAYS 0 **
		bit 5:	0 = allow RR rom when MMC BIOS disabled , 1 = disable RR ROM (R/W)	(***)
		bit 6:	0 = SPI write trigger mode, 1 = SPI read trigger mode (R/W)
		bit 7:	** ALWAYS 0 **
 
(*) 	Enabling MMC Bios sets ROM banking to the last 64K bank
(**) 	This bit also controls the green activity LED.
(***)	When in MMC64 bios mode, bit 5 controls RAM banking (0 = $e000 - $ffff, 1 = $8000 - $9fff)
			When in 16K mode, bit 5 enables RAM at $a000 - $bfff
 
$DF12:	MMC status register
		-----------------------
		bit 0:	0 = SPI ready, 1 = SPI busy (R)						
						1 = forbid ROM write accesses (W) (*)
 
		bit 1:	feedback of $DE00 bit 0 (GAME) (R)					
		bit 2:	feedback of $DE00 bit 1 (EXROM) (R)
		bit 3:	0 = card inserted, 1 = no card inserted (R)
		bit 4:  0 = card write enabled, 1 = card write disabled (R)
 
		bit 5:	EEPROM DATA line / DDR Register (R/W) (**)
		bit 6:	0 = RR compatibility mode, 1 = Extended mode (W) (***)
		bit 7:	EEPROM CLK line (W)
 
(*) Setting this bit will disable writes to ROM until next reset.
(**) Setting DATA to "1" enables reading data bit from EEPROM at this position.
(***) Selecting RR compatibility mode limits RAM to 32K and
		disables writes to extended banking register.
		Selecting Extended mode enables full RAM banking and enables
		Nordic Power mode in RR mode.
 
$DF13:	Extended banking register (*)
		-----------------------------
		bit 0:	bank address 16	(R/W)
		bit 1:	bank address 17 (R/W)
		bit 2:	bank address 18 (R/W)
		bit 3:	** ALWAYS 0 **
		bit 4:	** ALWAYS 0 **
		bit 5:	16K rom mapping (R/W)
		bit 6:	1 = enable RR register
		bit 7:	** ALWAYS 0 **
 
(*) Can only be read/written to when bit 6 of $DF12 is 1.
 
 
Notes for poor developer souls ;)
---------------------------------
This documentation is complete, nevertheless, since we aimed at compatibility to
all kinds of cartridges, the register map is quite complex, and we expect deve-
lopers to have certain problems understanding the various meanings. This is why
I describe now the basic 3 function modes of the MMC-Replay, from which 2 are
meant to be used by the developers.
 
C64 standard mode
-----------------
$df11: bit 0 = 1
$df13: bit 5 = 0
 
In this mode, GAME and EXROM are disabled. However, IO Ram/Rom banking is still
active.
 
 
MMC Replay Bios mode
--------------------
$df11:	bit 0 = 0
 
You are in MMC-Replay BIOS Mode. This mode is only intended for official Bios
development, and is thus no further discussed here.
 
Retro Replay mode
-----------------
$df11:	bit 0 = 1
				bit 5 = 0
$df13:	bit 5 = 0
 
You are in Retro Replay compatible mode. This mode is designed to work exactly
like a Retro Replay which is plugged into a MMC64. That means GAME/EXROM is
active, and RAM/ROM banking works normally. Extended banking registers at $df13
are active, HOWEVER, since the flash tool is designed to flash in 64K banks, it
is recommended not to use them, and try to make your ROM work in a single 64K
bank. If that is not possible, then please split your ROM in multiple 64K parts,
and advise the user to flash them in consecutive 64K banks. Read $df13 to deter-
mine your position in the 512k ROM, and calculate fom this point the position(s)
of the next 64K bank(s) of your ROM.
 
Super Mapper mode
-----------------
$df11:	bit 0 = 1
$df13:	bit 5 = 1
 
You are in 16k Super Mapper Mode. This mode is designed to define an enhanced
Retro Replay mode, in which you have 16k ROM/RAM banking at $8000-$bfff and
512 byte Ram/Rom banking at $de00-$dfff. GAME/EXROM works like in Retro Replay
mode. Banking bit A13 is disabled, since only 16K banks are selected in this
mode. This mode also defines 2 different RAM modes. Lets assume we have RAM
enabled (bit 5 of $de00 = 1):
 
Explaining the mapping of the Super Mapper mode
-----------------------------------------------
 
$df11: bit 5 = 0 (16k RAM/ROM mixed mode)
-----------------------------------------
$8000	----------------------------------
			8K RAM bank lo
$a000 ----------------------------------
			8K FLASH ROM bank hi
$c000 ----------------------------------
 
$df11: bit 5 = 1 (16k RAM mode)
-----------------------------------------
$8000	----------------------------------
			8K RAM bank lo
$a000 ----------------------------------
			8K RAM bank hi
$c000 ----------------------------------
 
Super Mapper mapping in freeze mode
-----------------------------------
 
In freeze mode, the memory map is different than Retro Replay:
 
$de00: bit 5 = 0
----------------
$de00 - $dfff (minus registers): 512 byte ROM area (mirrored from $9e00-$9fff)
 
$de00: bit 5 = 1
----------------
Disables any memory at $de00-$dfff due to CPLD routing problems. This is however
no problem, since RAM is always enabled at $8000-$9fff if you need it.
 
$df11: bit 5 = 0
----------------
$8000 - $9fff: 8K RAM bank low
$e000 - $ffff: 8K RAM bank hi
 
$df11: bit 5 = 1
----------------
$8000 - $9fff: 8K RAM bank lo
$e000 - $ffff: 8K FLASH rom bank hi
 
NOTES
-----
Banking bits A13-A15 are cleared when freeze is pressed.
Ram is always enabled in freeze mode. The Ram bit ($de00 bit 5) however is reset
$df11 bit 5 is not changed when freeze, meaning: you can put freeze code in ram!
Allowbank masks only banking bits A13-A15 in Super Mapper mode.
Every bit in $de01 can always be altered in Super Mapper mode.
 
Last words of advice
--------------------
DON'T MESS WITH THE EEPROM! People will get angry at you when trying to demon-
strate your "l337n355" by destroying or manipulating configuration data. The
contents of the EEPROM are checksummed, that means: DON'T TOUCH A SINGLE BYTE!
 
EEPROM is only accessible in MMC Replay Bios mode. Again: don't touch it!
 
The MMC-Replay Bios sets the following configurations:
ACTION REPLAY : Allowbank = 0, $df10-$df13 registers disabled. Nordic Power on.
RETRO REPLAY: $de01 unset, $df10-$df13 registers disabled
SUPER MAPPER: 16K mode, Standard cart mode, $df10-$df13 registers enabled
 
Freeze DOES NOT CLEAR banking bits 16-18.
 
$df13 can only be READ AND WRITTEN if bit6 of $df12 = 1.
 
Disabled register free the I/O memory which is underneath them.
 
Disabling RR Register disables ALL ROM/RAM banking too.